Moore's Law Just Took a Vertical Turn
- Rich Washburn
- 4 hours ago
- 10 min read
Updated: 3 hours ago
We spent decades asking how much smaller a transistor could get. IBM just changed the question: how high can we build?
Every once in a while, a technology story lands and a bunch of things we have been talking about for years suddenly stop looking like separate stories.
They become one story.
IBM's new 7-angstrom NanoStack technology did that for me.
At first glance, the headline is exactly what you would expect from the semiconductor industry: IBM breaks the 1-nanometer barrier. Nearly 100 billion transistors in an area roughly the size of a fingernail. Another node. Another record. Another absurdly small number. Except that isn't really what happened. The important part isn't that IBM went smaller.
IBM went up.
Instead of treating semiconductor scaling as primarily an X-and-Y problem — shrinking and packing transistors across a flat plane — IBM started exploiting the Z-axis. Transistors stacked vertically. One above another. And suddenly a conversation we have been having since 2023 looks very different.
This isn't an "I told you so." If anything, I find it humbling. Because looking backward, the breadcrumbs were everywhere. We just didn't know yet what they were assembling into.
2023: The Nanometer Race Starts Running Out of Road
Back in December 2023, we were talking about the Great Nanometer Chip Race.
At the time, the story was still largely framed around TSMC, Intel, Samsung, China and the geopolitical race to manufacture ever-smaller semiconductor nodes. But underneath that race was a more interesting problem. Traditional miniaturization was getting brutally difficult. The easy version of Moore's Law — shrink the transistor, put more of them on the chip, automatically get better economics and performance — was beginning to lose some of its magic. And something strange was happening.
Packaging was becoming important.
For most people, "chip packaging" sounds like the box the processor comes in. It isn't. Advanced packaging is increasingly about how multiple pieces of silicon, memory and specialized compute are physically connected into a larger computational system.
In that 2023 conversation, we were already looking at packaging moving from something that happened after the important semiconductor engineering to something becoming part of the important semiconductor engineering itself. That was the first block. The chip was starting to become more than the chip.
2024: Engineers Begin Rearranging the Machine
Then things got more interesting. In May 2024, we were talking about two technologies that sounded esoteric at the time: Nanosheet transistors. And Backside power delivery.
Gate-all-around nanosheet transistors replaced the older FinFET geometry by surrounding the transistor channel more completely with the gate, giving engineers better electrostatic control as dimensions became ridiculously small. But backside power was the thing that really caught my attention. Instead of cramming both electrical power and signal routing onto the same side of the silicon, engineers essentially said: Why? Move the power delivery network to the back. Free the front for signals. Reduce congestion. Shorten paths. Improve efficiency.
Once again, the interesting thing wasn't merely another shrink. Engineers were rearranging the physical structure of the computer to keep progress moving. And somewhere in that discussion was a phrase that now seems almost embarrassingly obvious: Architecture compensating for physics. Remember that one. Because it may be the whole story.
2024: Then Physics Started Getting Weird
A few months later, we went another layer down. Materials. Quantum mechanics. Tunneling.
At extremely small dimensions, electrons stop respecting the nice clean barriers engineers created for them. They tunnel. They leak. They generate heat. Things that were once rounding errors become engineering problems. So researchers started looking at different materials and different transistor concepts — including devices designed around quantum tunneling rather than merely treating tunneling as an unwanted side effect.
Again: Architecture compensating for physics. Materials compensating for physics. Geometry compensating for physics. This was starting to look less like a race toward a smaller transistor and more like an industry gradually rewriting the definition of a transistor.
2025: "Okay, But What If We Actually Hit the Wall?"
Then one night the conversation got weird. Literally. In The Night the Future Got Weird, we played with a thought experiment: What happens if Moore's Law really does hit the wall? No more easy shrink. No more automatic performance gains. No more free acceleration.
The conclusion wasn't particularly pessimistic. Actually, it was the opposite. If physics removes brute-force scaling as the easy answer, human ingenuity becomes more valuable. And one of the examples we landed on was CFET — complementary transistors vertically stacked instead of simply arranged next to each other. The point wasn't that progress ends.
The point was that when one geometry stops working, engineers change the geometry.
That article put it another way: Physics establishes the boundary. Engineering finds the loophole. At the time it was part semiconductor analysis, part thought experiment and part Wednesday-night rabbit hole. Eight months later, IBM opened the Z-axis.
2026: The Angstrom Era
Then this May we were talking about The Angstrom Era. By that point the problem was becoming much easier to see. AI wants compute at a rate conventional semiconductor scaling simply isn't delivering.
The old playbook was: Build a better chip. Then another better chip. Then connect a whole lot of them together. But the bottleneck was shifting. Increasingly the important questions were becoming: How do you package them? How do you power them? How do you cool them? How do you move data between them? How close can memory sit to compute? How much useful computation can you extract from every watt entering the facility?
The competitive frontier was moving outward from the transistor and into the system architecture. We described TSMC as essentially building a bigger city while Intel was trying to invent a better brick. Still like that one. But IBM just added another dimension to the city.
IBM: Cool. We're Going Vertical.
On June 25, 2026, IBM announced its 7-angstrom — or 0.7-nanometer-class — semiconductor research technology.
Important caveat first: "0.7 nanometer" does not mean IBM fabricated some important transistor feature exactly 0.7 nanometers wide. Modern process-node names stopped being literal physical dimensions a long time ago. The interesting part is the architecture underneath the number.
IBM calls it NanoStack. And IBM describes the idea almost exactly as you would hope: Instead of continuing to scale only across the X- and Y-axis, what if semiconductor engineers start scaling into the Z-axis?
The architecture vertically stacks complementary nanosheet transistors. Rather than putting the N-type and P-type devices beside one another, IBM fabricates transistor structures on separate wafers and bonds them into an extremely tight multilayer structure.
The result is what IBM describes as a true 3D transistor. Not chips stacked on chips. Not merely memory packages stacked over processors. Transistors stacked over transistors. That distinction matters.
We Didn't Run Out of Road. We Found Another Axis.
For sixty years, semiconductor scaling was predominantly a land-use problem. How many houses can you fit into the neighborhood? Make the houses smaller. Move them closer together. Improve the roads. Repeat.
But eventually you can't make the lots infinitely small. So somebody finally asks the question every city eventually asks: Why are we only building one-story buildings?
That's NanoStack.
And suddenly Moore's Law begins looking less like a law about shrinking things and more like a law about increasing computational density through whatever engineering means remain available.
IBM reports that its NanoStack approach roughly doubles transistor density compared with its earlier 2 nm research technology. It has experimentally demonstrated the architecture through wafer bonding, dual-channel engineering and a functioning CMOS inverter. IBM says it sees a path toward commercial adoption in as little as five years, although that is very different from saying mass-production chips exist today.
There is still enormous manufacturing risk. Alignment. Yield. Bonding defects. Heat. Routing. Cost. Equipment. Scaling a research demonstration into millions of reliable processors is one of the hardest things humans manufacture.
So no, your next NVIDIA GPU isn't suddenly going to have IBM NanoStack transistors in it. But that's almost beside the point. The direction has changed.
The Real Breakthrough May Be the Freedom
There is another fascinating consequence to building vertically. IBM says the different transistor layers can use different channel-material combinations and be optimized independently for performance or power efficiency.
Think about that. Going vertical doesn't merely give engineers more space. It gives them more degrees of freedom. Different materials. Different electrical characteristics. Different optimizations. Different functions.
Suddenly the transistor stack starts behaving less like a tiny component and more like an engineered structure. That matters because the future of computing increasingly looks heterogeneous. Not one perfect transistor. Not one perfect processor. Different computational structures optimized for different workloads and physically assembled into increasingly intimate architectures. Which is exactly what the AI era needs.
Then There's the Number I Can't Stop Looking At
Forget 0.7 nanometers for a minute. Forget 100 billion transistors. Forget the headline.
Look at this: 40 percent SRAM scaling.
IBM reports roughly 40% scaling in SRAM with NanoStack — an area where density improvement has been particularly stubborn. IBM specifically connects that improvement to the high-bandwidth data demands of advanced AI workloads.
That may ultimately matter more than the transistor-count headline. Because one of the central problems in AI computing isn't actually computation. It's movement.
Moving weights. Moving activations. Moving cache. Moving information between processors. Moving information between processors and memory. Moving information between packages. Moving it across boards. Across racks. Across networks.
Every movement costs something. Latency. Energy. Heat. Infrastructure. Money.
We have spent decades optimizing the cost of computation. Increasingly, we need to optimize the distance computation requires information to travel. And that changes how I think about the next generation of AI hardware.
The Next Compute Revolution May Be About Eliminating Distance
Logic closer to memory. Memory closer to accelerators. Cache closer to logic. Power delivered through a separate plane. Optics pushed closer to compute. Processors connected through advanced packaging. Different transistor materials stacked vertically.
More of the machine collapsing physically toward the place where computation occurs. Because eventually distance itself becomes an engineering tax. The farther an electron — or photon — has to travel, the more infrastructure exists simply to move information rather than operate on it. And when AI systems are performing incomprehensible numbers of those movements every second, tiny inefficiencies become megawatts. Then tens of megawatts. Then hundreds.
This is where the semiconductor story suddenly becomes a data-center story. And a power story. And a cooling story. And a capital story. Those aren't separate domains anymore. They're one optimization problem.
The Blocks Were Falling Together
Looking back, the lineage now feels almost comically clean.
2023: The nanometer race is approaching physical limits. Advanced packaging starts becoming part of the computational architecture.
2024: Nanosheets and backside power delivery begin physically reorganizing the transistor and the chip.
2024: New materials and quantum behavior force us to reconsider the assumptions underneath conventional silicon devices.
2025: We ask what happens when Moore's Law actually hits the wall — and end up talking about CFETs, stacked transistors and changing the geometry of the problem.
2026: The Angstrom Era makes it increasingly obvious that system architecture, power, memory, packaging, cooling and data movement are becoming as strategically important as transistor scaling itself.
IBM: Cool. We're going vertical. And somehow all of those individual blocks start looking like parts of the same machine.
Moore's Law Didn't Die. It Changed Direction.
Maybe we've been asking the wrong question. People have spent years debating whether Moore's Law is alive or dead. Maybe neither answer is particularly useful.
The thing that's dying is the assumption that semiconductor progress must come primarily from continuously shrinking a two-dimensional transistor layout. That was one extraordinarily productive chapter. But it doesn't have to be the whole book.
We are entering a world of: 3D transistor architectures. Advanced packaging. Backside power. Chiplets. Co-packaged optics. New channel materials. High-bandwidth memory. Vertical integration. Novel cooling. Photonic interconnects. And increasingly sophisticated system-level design.
None of these technologies alone replaces traditional scaling. Together, they redefine what scaling means. The industry isn't abandoning Moore's Law. It's becoming more creative about where the additional computation comes from.
Architecture compensating for physics. That may be the phrase I keep. Because the closer we get to physical limits, the less progress becomes automatic. The next generation of performance has to be engineered from every dimension of the system. And That Changes the AI Infrastructure Equation
From the AI infrastructure side, this is why NanoStack matters even years before commercial deployment. We tend to talk about AI capacity in GPUs.
How many H100s? How many Blackwells? How many Rubins? How many megawatts? But those are snapshots of particular architectures at particular moments in semiconductor history. The deeper metric is: How efficiently can you turn electricity into useful computation?
That depends on the entire machine. Transistors. Memory. Packaging. Interconnect. Networking. Power conversion. Cooling. Software. Utilization.
Architecture. And increasingly, geometry.
If vertical transistor architectures shorten distances, increase density, improve local memory and create new opportunities for heterogeneous integration, then the implications eventually propagate all the way out to the data center. More useful compute per wafer. More compute per package. More compute per rack. More compute per megawatt. Potentially more compute per dollar of infrastructure.
That is why this isn't merely an IBM semiconductor story. It's another signal that the physical substrate of AI is being reconstructed underneath us.
The Chip Is Becoming the System
That may ultimately be the biggest idea here. The historical boundaries are dissolving. The transistor was inside the chip. The chip was inside the package. The package was on the board. The board was in the server. The server was in the rack. The rack was in the data center. Nice clean hierarchy.
Increasingly those layers influence one another so strongly that treating them independently makes less sense. Memory architecture affects processor performance. Packaging determines interconnect. Interconnect determines power. Power determines cooling. Cooling determines density.
Density determines building design. Building design determines economics. And the economics determine what AI can actually be deployed.
The entire stack becomes one machine. So when IBM changes the geometry of the transistor, somewhere down the line it may change the economics of the data center. That is how connected this has become.
One Final Thought
There is something wonderfully human about all of this. We finally begin approaching a boundary imposed by nature. Atoms. Quantum mechanics. Heat. The actual physical stuff of the universe saying: You can't keep doing it this way forever. And engineers respond: Okay. What about sideways? What about underneath? What about different materials? What about light? What about stacking them? What about up?
That's the part that humbles me. Not that we somehow "called" IBM's NanoStack. We didn't. It's that we kept following the individual pressure points — packaging, power, materials, geometry, memory, interconnect — and they kept leading toward the same conclusion: The age of free improvement is giving way to the age of architectural ingenuity.
Physics isn't stopping computation. It's making us earn it. For decades, Moore's Law drove us relentlessly downward. Smaller. Smaller. Smaller.
And now, just when it looked like we might finally be running out of room: IBM looked at the wall and apparently asked a very different question. How high is the ceiling?
Maybe Moore's Law didn't die. Maybe it just took a vertical turn.
Rich Washburn is a technologist, strategist, and Founder & Chief AI Architect of ARIA AI Labs, working at the intersection of AI, infrastructure, communications, and capital. He also serves as Managing Partner and Chief AI Officer at Eliakim Capital.
Sources & Further Reading
IBM Research
Earlier Work in This Series
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