China Cannot Build NVIDIA's Best Chip — So It Is Trying to Make the Chip Matter Less
- Rich Washburn
- 17 hours ago
- 7 min read
For years, the semiconductor story was told in nanometers. 14nm, 7nm, 5nm, 3nm. Each shrink meant more transistors per square millimeter, more performance per watt, more compute per dollar. The country that controlled the smallest transistors controlled the future.
That story is still true — for the part of the system that does the math. But AI systems are no longer merely chips. They are compute, memory, packaging, networking, power, cooling and software functioning as one machine. And the bottleneck is shifting from doing the math to moving the data.
A company called DFSX is attacking that bottleneck with 14nm silicon and vertically bonded memory and compute. Its planned TY64 rack claims 960 TB/s of aggregate memory bandwidth, versus 576 TB/s for NVIDIA's GB200 NVL72 — about 67% more, not literally twice as much. The catch: the DFSX number is a claimed specification for a planned system, not an independently benchmarked result. It also has substantially less raw compute than Blackwell. So this does not prove that a 14nm Chinese system beats NVIDIA. It suggests that, for memory-bound inference, clever packaging may partially offset a major process-node disadvantage. That is a much bigger story than "China beats NVIDIA."
The bottleneck moved
Here is the thing nobody outside hardware engineering talks about much: the dominant cost in modern AI inference is not computation. It is data movement. Moving a byte from memory to the compute unit consumes more energy than operating on it. The further the data has to travel, the more you pay in latency, power and thermal overhead. As models get larger, the time spent shuffling weights between memory and compute dominates the time spent actually multiplying matrices.
This is why NVIDIA sells NVLink, why HBM is stacked directly on the package, and why everyone in the industry is obsessed with memory bandwidth. The problem is no longer "can we do the math fast enough." The problem is "can we feed the math fast enough."
NVIDIA's response is to build the most advanced chips possible and surround them with the fastest memory possible and the fastest interconnects possible. That works. It is also extraordinarily expensive and depends on access to leading-edge fabrication at TSMC.
DFSX is responding to restricted access to that fabrication by reorganizing the machine around memory bandwidth, hybrid bonding and rack-scale architecture. It is effectively saying: fine. You control the smallest transistors. We'll attack the distance the data has to travel.
The revenge of the mature node
This is what I mean by the revenge of the mature node. Export controls restricted China's access to leading-edge fabs. The assumption was that this would lock China out of competitive AI hardware indefinitely, because the node gap would compound over time.
But the node gap only compounds if the node remains the decisive variable. If the bottleneck shifts from transistor density to memory bandwidth, and if memory bandwidth can be improved through packaging, interconnect and architecture rather than transistor shrinkage, then the node becomes less decisive. Not irrelevant. Not obsolete. Less monopolistically decisive.
DFSX is not winning the nanometer race. It is trying to change which race matters.
That is a fundamentally different strategy than trying to catch up to TSMC. It says: we accept that we cannot build the smallest transistors. We will build a system where the size of the transistor matters less than the architecture around it. 14nm silicon with vertically bonded memory and compute is the embodiment of that strategy. You take the process node you have access to, and you compensate by collapsing the distance between memory and compute, by integrating at the rack level rather than the chip level, and by designing the system as if the interconnect is the product.
What the numbers actually say
Let's be careful with the numbers, because the marketing is already getting ahead of the engineering. DFSX claims 960 TB/s of aggregate memory bandwidth for the TY64 rack. NVIDIA's GB200 NVL72 delivers 576 TB/s. That is about 67% more bandwidth for the DFSX system. But bandwidth alone does not equal tokens per second. A system with more memory bandwidth but less compute may be faster on memory-bound workloads and slower on compute-bound workloads. Whether DFSX's architecture actually translates claimed bandwidth into real inference performance is an open question that will not be answered until independent benchmarks exist.
The system also has substantially less raw compute than Blackwell. For compute-bound workloads — training, certain inference patterns — the raw FLOPS still matter, and Blackwell's advantage there is enormous. So the honest framing is: DFSX has an architectural thesis, a promising packaging approach, and paper specifications that suggest it may be competitive on a specific class of memory-bound inference workloads. It has not yet proven that thesis in production. This is an architectural warning shot. Not a Blackwell killer.
Why the warning shot matters
Here's where it gets interesting, and why this article is not really about DFSX. The warning shot matters because it reveals a path that export controls may not close. If you restrict access to the smallest transistors, and the response is to redesign the system so that transistor size matters less, then the control mechanism attacks a variable that is becoming less decisive. Export controls are accelerating architectures that make leading-edge nodes less decisive.
That sentence should make policymakers uncomfortable. It does not mean export controls failed. It means they may have a shorter half-life than expected, because they incentivize exactly the kind of architectural innovation that erodes the advantage they were designed to protect.
This is a pattern that repeats throughout technology history. You restrict access to a specific capability. The restricted party innovates around the restriction. The workaround changes the architecture enough that the original capability becomes less critical. The control still works — you are still preventing them from building 3nm chips — but the strategic value of preventing them from building 3nm chips declines because the system no longer depends as heavily on 3nm chips. The analog is not perfect, but it rhymes with what happened with surveillance and encryption. You restrict access to strong crypto. People build systems where the crypto is embedded in the architecture rather than the application. The control works — you can still restrict the algorithm — but the system protects itself through structure rather than through the specific mechanism you controlled.
The system is the product
The deeper point here is one I keep arriving at from different directions: AI systems are no longer chips. They are machines. The chip is a component. The machine is the product. NVIDIA understands this. That is why NVLink, NVSwitch, DGX and the entire rack-scale architecture exist. NVIDIA does not sell chips. It sells integrated systems where the chip is one element in a carefully engineered balance of compute, memory, interconnect, power and software.
DFSX is attempting the same thing from the other end. Instead of starting with the best chip and engineering outward, it is starting with a mature node and engineering inward — collapsing the distance between memory and compute, bonding them vertically, and treating the rack as the unit of design rather than the processor.
Both approaches are converging on the same conclusion: the system is the product. The difference is that NVIDIA reaches that conclusion from the top of the process hierarchy, and DFSX is trying to reach it from the middle. Whether DFSX succeeds commercially is almost beside the point. The architectural strategy is sound, the bottleneck it targets is real, and the incentive structure created by export controls ensures that more companies will attempt similar approaches. Some of them will get it right.
What this means for the infrastructure thesis
I have been writing for months about AI infrastructure as the next scarcity layer. Power, cooling, compute, land, water, fiber. The thesis is that as models get larger and deployment gets more distributed, the physical infrastructure underneath becomes the binding constraint.
DFSX adds another dimension to that thesis. The infrastructure is not just physical — power and cooling and land. It is also architectural. How you package memory and compute, how you interconnect them, how you manage the distance data travels — that is infrastructure too. It is the infrastructure inside the machine. And if the bottleneck is moving from transistors to data movement, then the companies and countries that excel at architectural innovation — packaging, bonding, interconnect, rack-scale design — may gain leverage that partially compensates for a disadvantage in process-node access.
This does not make leading-edge fabrication unimportant. TSMC's 3nm and 2nm nodes will continue to set the ceiling for what is possible. But the floor — the minimum viable architecture for competitive AI inference — may be reachable through clever integration rather than raw transistor density. That is the strategic implication. The gap between the ceiling and the floor may be narrowing. And export controls may be accelerating exactly the innovation that narrows it.
The race that matters
Here is the uncomfortable question for U.S. policy. If export controls accelerate architectural innovation that makes process nodes less decisive, then the controls have a strategic half-life. They buy time, but the time they buy is determined by how quickly the restricted party can innovate around the constraint — and AI is accelerating that innovation curve.
The same logic that makes AI dangerous in cybersecurity — compression of time and cost for existing capabilities — makes it dangerous in hardware design. If AI-assisted design tools can accelerate packaging innovation, interconnect design and system-level optimization, then the workaround to export controls gets faster to build. The policy question is not "how do we prevent China from building 3nm chips." That question has an answer, and the answer is working.
The policy question is "what happens when building 3nm chips is no longer the only way to build competitive AI systems." That question does not have an answer yet.
DFSX is not the answer. It is the first clear signal that the question is being asked.
The race is no longer just about who builds the smallest transistors. It is about who builds the system where the size of the transistor matters less. China cannot build NVIDIA's best chip. It knows this. So it is trying to make the chip matter less.
If that strategy works — even partially — it changes the geometry of the semiconductor competition in ways that export controls were not designed to address.
You can restrict access to a process node. You cannot restrict access to an idea whose time has come.
Rich Washburn is a technologist and strategist working at the intersection of AI, infrastructure, and capital. He is Managing Partner and Chief AI Officer at Eliakim Capital.